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Assembly Language
system control instructions
summary
This web page examines system control instructions in assembly language. Specific examples of instructions from various processors are used to illustrate the general nature of assembly language.
For those with high speed connections, the very large single file summary is still on line.
system control
System control instructions control some basic element of the system or processor state.
Many system control instructions are privileged, meaning that only certain trusted routines are allowed to use them. This is implemented by having privilege states. The most simple version is two states: user and supervisor states. The user state can’t run any privileged instructions, while the supervisor state can run all instructions. Some processors have more than two privilege states, allowing greater granularity of freedom to increasingly trusted operations.
The most basic kind of system control instructions are those that modify the condition codes or user portion of a status register.
Closely related are instructions that modify an entire status word or status register. The more powerful version is a privileged instruction and includes access to portions of the status register that can control or modify other processes.
Machine control instructions directly affect the entire processor. Stop or halt instructions bring the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset, or external action.
Reset instructions reset the processor. This may include any or all of: setting registers to an initial value, setting the program counter to a standard starting location (restarting the computer), clearing or setting interrupts, and sending a reset signal to external devices.
Trap generating instructions generate a system trap. This includes a transition to a privileged state and turns control over to a routine with supervisor permission. This allows user processes to communicate with and make requests of the operating system. Note that it is common for some parts of an operating system to run in normal user mode so as to limit potential damage if something goes wrong.
Memory management instructions control memory and how memory is mapped and accessed by user and system routines. These instructions are almost always privileged and vary greatly from processor to processor (although the general capabilities and effects are pretty standard).
- MOVE <ea>, CCR Move to Condition Codes Register; Motorola 680x0, Motorola 68300; moves data from data register, memory, or immediate data to user condition codes register
- MOVE CCR, <ea> Move from Condition Codes Register; Motorola 680x0, Motorola 68300; moves data from user condition codes register to data register or memory
- ANDI #data, CCR And Immediate to Condition Codes Register; Motorola 680x0, Motorola 68300; logical AND of the immediate data with the user condition codes register
- ORI #data, CCR Or Immediate to Condition Codes Register; Motorola 680x0, Motorola 68300; logical inclusive OR of the immediate data with the user condition codes register
- EORI #data, CCR Exclusive Or Immediate to Condition Codes Register; Motorola 680x0, Motorola 68300; logical exclusive OR of the immediate data with the user condition codes register
- MOVE <ea>, SR Move to Status Register; Motorola 680x0, Motorola 68300; moves data from data register, memory, or immediate data to entire status register; privileged instruction (supervisor state)
- MOVE SR, <ea> Move from Status Register; Motorola 680x0, Motorola 68300; moves data from entire status register to data register or memory; privileged instruction (supervisor state)
- ANDI #data, SR And Immediate to Status Register; Motorola 680x0, Motorola 68300; logical AND of the immediate data with the entire status register; privileged instruction (supervisor state)
- ORI #data, SR Or Immediate to Status Register; Motorola 680x0, Motorola 68300; logical inclusive OR of the immediate data with the entire status register; privileged instruction (supervisor state)
- EORI #data, SR Exclusive Or Immediate to Status Register; Motorola 680x0, Motorola 68300; logical exclusive OR of the immediate data with the entire status register; privileged instruction (supervisor state)
- MOVE USP Move User Stack Pointer; Motorola 680x0, Motorola 68300; moves the contents of the user stack pointer to or from the specified address register; privileged instruction (supervisor state)
- MOVEC Move Control Register; Motorola 680x0, Motorola 68300; moves the contents of the specified address or data register to the specified control register or moves the contents of the specified control register to the specified data or address register (zero filled to 32 bits), control registers: Source Function Code (SFC) register, Destination Function Code (DFC) register, Cache Control Register (CACR), User Stack Pointer (USP), Vector Base Register (VBR), Cache Address Register (CAAR), Master Stack Pointer (MSP), Interrupt Stack Pointer (ISP); privileged instruction (supervisor state)
- MOVES Move Address Space; Motorola 680x0, Motorola 68300; moves information between address spaces (allowing data communication across process boundaries), either moving data (8, 16, or 32 bits) from a specified address or data register to a memory location in the address space specified by the destination fucntion code (DFC) register or moves date (8, 16, or 32 bits) from a memory location in the address space specified by the source function code (SFC) register to the specified data or address register; does not modify flags; privileged instruction (supervisor state)
- STOP Stop; Motorola 680x0, Motorola 68300; loads an immediate operand into the program status register (both user and supervisor portions), advances program counter to next instruction, and stops the processor from fetchhing and executing instructions; privileged instruction (supervisor state)
- LPSTOP Low Power Stop; Motorola 68300; loads an immediate operand into the program status register (both user and supervisor portions), advances program counter to next instruction, and stops the processor from fetchhing and executing instructions, the new interrupt mask is copied to the external bus interface (EBI), internal clocks are stopped, the processor remains stopped until a trace, higher interrupt than new mask, or reset exception occurs; privileged instruction (supervisor state)
- RESET Reset External Devices; Motorola 680x0, Motorola 68300; asserts the NOT RESET signal for 512 clock periods, resetting all external devices, no internal changes other than incrementing program counter to the next instruction; privileged instruction (supervisor state)
- RTE Return from Exception; Motorola 680x0, Motorola 68300; transfers the value at the top of the system stack into the status register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer by a displacement value designated by format mode (effectively deallocating temporary storage space from the stack, the amount of space varying by type of exception that occurred), and changes program flow to the return address; privileged instruction (supervisor state)
For those with high speed connections, the very large single file summary is still on line.
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Created: February 21, 2001 (from machcode.htm)
Last Updated: February 21, 2001
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